This relates to N-well or P-well strap structures for use in integrated circuits.
N-well or P-well strap structures are typically used in integrated circuits to tie a source line to a well region so as to assure that the voltage in the well region is the same as the voltage at the source line.
FIGS. 1 and 2 depict a top view and a cross-section along lines 2-2 of FIG. 1 of a typical integrated circuit structure 100 that includes an active device and a well strap formed in a well in a semiconductor substrate 105 It will be understood that this structure may be replicated multiple times in the integrated circuit. Structure 100 includes source and drain regions 110, 120 formed in a well 130 with a polysilicon gate finger 140 formed on a dielectric layer (not shown) on the surface of well 130. These elements will be recognized as forming a MOS transistor; but it is to be understood that the MOS transistor is only illustrative of any active device. Following industry practice, the length L of gate 140 is its shorter dimension.
Structure 100 further includes diffusion region 160 that makes ohmic contact with well 130 and ohmic contacts (or taps) 115 to source region 110, ohmic contacts 125 to drain region 120, and ohmic contacts 165 to diffusion region 160. The diffusion region 160 and its contacts or taps 165 constitute the well strap. A shallow trench isolation (STI) region 150 surrounds the active device and well strap.
Illustratively, the transistor is a PMOS transistor, source and drain regions are P-type, well 130 is an N-type well, and diffusion region 160 is N-type. Alternatively, the transistor is an NMOS transistor, source and drain regions 110, 120 are N-type, and well 130 and diffusion region 160 are P-type.
In certain prior art integrated circuits, the N-well or P-well strap is placed so that it is directly abutting an active device such as the MOS transistor as shown in FIGS. 1 and 2. Further details concerning such an implementation of a N-well strap may be found in U.S. Pat. No. 7,586,147B2 for “Butted Source Contact and Well Strap,” which is incorporated herein by reference. In alternative structures, the well strap may form a ring around the active device or group of active devices.
In certain other prior art integrated circuits, dummy polysilicon is placed next to the device gates so as to control uniformity of critical dimensions. In this case, the well strap is spaced apart from the active device. FIG. 3 is a top view of such a prior art integrated circuit structure 300 including an active device and a well strap. Illustratively, structure 300 includes source and drain regions 310, 320 formed in a well 330 with a polysilicon gate finger 340 formed on a dielectric layer (not shown) on the surface of well 330. These elements will be recognized as forming a MOS transistor; but it is to be understood that the MOS transistor is only illustrative of any active device. A substrate (not shown) similar to substrate 105 of FIG. 2 underlies well 330.
Structure 300 further includes diffusion region 360 that makes ohmic contact with well 330 and ohmic contacts (or taps) 315 to source region 310, ohmic contacts 325 to drain region 320, and ohmic contacts 365 to diffusion region 360. The diffusion region 360 and its contacts or taps 365 constitute the well strap. A STI region 350 surrounds the active device and the well strap. Again, the transistor can be a PMOS transistor with P-type source and drain regions 310, 320 and N-type well 330 and diffusion region 360; or the transistor can be a NMOS transistor with N-type source and drain regions 310, 320 and P-type well 330 and diffusion region 360.
Structure 300 further comprises dummy polysilicon gate fingers 371, 372 located on opposite sides of the active device above portions of the STI region 350. As a result, the well strap is separated from the active device by at least one length of the dummy polysilicon finger.
In certain other prior art integrated circuits, double dummy polysilicon is placed next to active devices. FIG. 4 is a top view of such a prior art integrated circuit structure 400 including an active device and a well strap. Illustratively, structure 400 includes on the left-hand side source and drain regions 410, 420 formed in a well 430 with a polysilicon gate finger 440 formed on a dielectric layer (not shown) on the surface of well 430. These elements will be recognized as forming a first MOS transistor; but it will be understood that the MOS transistor is only illustrative of any active device. A second MOS transistor is formed on the right-hand side of FIG. 4 and includes the same elements bearing the same numbers followed by the suffix A. Again, a substrate (not shown) similar to substrate 105 of FIG. 2 underlies well 430.
Structure 400 further includes diffusion region 460 that makes ohmic contact with well 430 and ohmic contacts (or taps) 415 to source region 410, ohmic contacts 425 to drain region 420, and ohmic contacts 465 to diffusion region 460. The diffusion region 460 and its contacts or taps 465 constitute the well strap. A STI region 450 surrounds the active devices and the well strap. Again, the transistor can be a PMOS transistor with P-type source and drain regions 410, 420 and N-type well 430 and diffusion region 460; or the transistor can be a NMOS transistor with N-type source and drain regions 410, 420 and P-type well 430 and diffusion region 460.
Structure 400 further comprises dummy polysilicon gate fingers 471, 472, 473, 474 with the first two fingers 471, 472 located above portions of STI region 450 between the well strap and the first transistor and the second two fingers 473, 474 being located above other portions of STI regions 450 between the well strap and the second transistor. As a result, the well strap is separated from the active device by at least two lengths of the dummy polysilicon fingers.